Did you know that OR and XOR return different answers when both inputs are true? This one row distinguishes two entire logic gates. Boolean logic is the language of true and false conditions inside computing systems, and the 2027 Computing syllabus expects students to turn circuit drawings into exact truth tables and expressions.
Ministry of Education V3.0 Reference 321 teaches the K349 G3 Computing Module 1.3 gates AND, OR, NOT, NAND, NOR and XOR, Boolean identities, De Morgan’s theorem and logic circuits with up to three inputs. It offers twenty-six original worked examples, a twelve-stage verification protocol, a complete two-input table, an original three-input circuit and eduKate Depth–Load–Transfer diagnostics.
The circuit and status examples are theoretical educational models. They are not real-world control designs, emergency mechanisms, or representations of a school’s security setup.
1. What Is a Logic Gate?
A logic gate takes one or more binary conditions and returns another binary value. One means the condition is true; zero means false. When several gates are connected, the intermediate result becomes the input for another decision. The result is precise only if the inputs retain the same meaning throughout.
2. Official 2027 G3 Computing K349 Module 1.3
The official SEAB 2027 Computing K349 syllabus, page 6 specifies converting Boolean statements and circuits, building truth tables with a maximum of three inputs, the six gates, Boolean associative/distributive rules and De Morgan’s theorem. This is distinct from Reference 301’s binary representation and general algorithm design.
3. Gate Meanings at a Glance
| Gate | What makes the result 1? |
|---|---|
| AND | Both inputs are 1 |
| OR | At least one input is 1, including both |
| NOT | Its one input is 0 |
| NAND | Not both inputs are 1 |
| NOR | Both inputs are 0 |
| XOR | Exactly one input is 1 |
4. Full Two-Input Truth Table
| A | B | AND | OR | NAND | NOR | XOR |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 |
Inspect the 1/1 row especially: OR gives 1, XOR gives 0, NAND gives 0 and NOR gives 0. All four outcomes are required by their definitions.
5. An Original Three-Input Truth Table
For the expression (A AND B) OR C, compute the AND subexpression first, then OR that result with C. Three binary inputs require eight rows, not six or seven.
| A | B | C | A AND B | Output |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 1 |
| 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 1 | 1 |
| 1 | 1 | 1 | 1 | 1 |
6. Eight Rooms of Boolean Reasoning
Room one names the input meanings. Room two counts binary possibilities. Room three identifies gates. Room four checks inversions. Room five respects grouping. Room six traces intermediate wires. Room seven verifies equivalence by all rows. Room eight interprets an unseen word problem without switching meanings.
7. Twelve-Stage Read–Trace–Verify Method
Stage 1 — Define input meanings
For every signal, explain what zero and one mean. A could stand for a booking flag or a switch state; changing its definition midway invalidates otherwise correct logic.
Stage 2 — Count the variables
The current K349 syllabus limits required circuit truth tables to three inputs. Two inputs create four rows and three create eight.
Stage 3 — Identify AND, OR and NOT
AND requires all true, inclusive OR requires at least one true, and NOT inverts a single binary value. Test them on 0/0 and 1/1 before moving on.
Stage 4 — Recognise NAND, NOR and XOR
NAND and NOR invert complete AND and OR results. XOR outputs one only when its two inputs differ, rather than whenever any input is true.
Stage 5 — Read gate symbols carefully
An inversion bubble at the end of a symbol changes the gate’s behaviour. A NAND drawing is not simply an AND gate with one arbitrarily inverted input.
Stage 6 — Write a parenthesised Boolean expression
Express a network in clear words or symbols: (A AND B) OR C is different from A AND (B OR C). Maintain consistent notation throughout.
Stage 7 — Work through intermediate signals
Calculate the output of the first gate before feeding it to the next. One intermediate column often locates a mistake faster than checking the final answer alone.
Stage 8 — Enumerate every binary combination
For three inputs use 000,001,010,011,100,101,110,111. Each row must appear exactly once, and no row should be silently skipped.
Stage 9 — Apply the named identity
Use laws such as idempotence, annulment, identity, distribution and De Morgan’s theorem only when the resulting expression preserves exactly the same output.
Stage 10 — Use a truth table to verify equivalence
Matching one example does not establish two circuits are equivalent. Check every row; one differing row is sufficient to disprove equivalence.
Stage 11 — Interpret the model’s meaning
Relate the Boolean result to the stated fictional scenario. A mathematically correct circuit can still be the wrong model if the meaning of a sensor signal is reversed.
Stage 12 — Transfer without copying a circuit
Test a new two- or three-input question and explain the gates, trace and truth table independently. A classroom paper circuit never certifies real machinery or emergency equipment.
8. A Fictional Classroom Status Indicator
An invented practice question defines A as an active booking, B as a supervising teacher present and C as an authorised teaching demonstration. Its paper indicator is one if (A AND B) OR C is true. This is a simplified educational condition, not an actual school access system. It helps learners move from English-language statements to a three-input truth table.
9. Twenty-Six Original Worked Boolean Examples
10. Worked Example A — AND with one false input
A=1, B=0 yields A AND B=0. The gate needs both inputs true, and the order of A and B does not change the result.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
11. Worked Example B — Inclusive OR
A=1, B=0 yields A OR B=1. A=1 and B=1 would also yield 1; inclusive OR is true if at least one input is true.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
12. Worked Example C — XOR with two true values
A=1, B=1 yields A XOR B=0. Since the inputs match, the exclusive choice is false; this differs from OR.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
13. Worked Example D — NAND with two true values
A=1, B=1 yields AND=1 then NAND=0. The output inversion is the defining feature.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
14. Worked Example E — NOR with two false values
A=0, B=0 yields OR=0 then NOR=1. It returns one only when neither input is true.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
15. Worked Example F — NOT on one input
A=0 yields NOT A=1; if A is one, the output would be zero. NOT takes one input, not a two-input pair.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
16. Worked Example G — NAND with a zero
A=0 and B=1 give AND=0 and NAND=1. Don’t decide that every NAND row equals one: the 1/1 row is different.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
17. Worked Example H — XOR with two zero values
A=0 and B=0 give XOR=0. The exclusive gate is false when the inputs agree even if both are false.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
18. Worked Example I — Three-input AND
A=1, B=1, C=0 yields zero because the all-true requirement is not met. One false input prevents a three-input AND from producing one.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
19. Worked Example J — Three-input OR
A=0, B=0, C=1 yields one. The one true input suffices, even though the other two are false.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
20. Worked Example K — A followed-by gate
For A=1,B=0,C=1, (A AND B) OR C gives 0 OR 1=1. Calculate the parentheses first.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
21. Worked Example L — A second grouping
For A=1,B=0,C=1, A AND (B OR C) gives 1 AND 1=1. Matching the previous result on this one row is not proof of equality for all rows.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
22. Worked Example M — A counterexample to false equivalence
Take A=0,B=1,C=1. The expression A AND(B OR C) gives 0 but (A AND B) OR C gives 1. Their logic differs.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
23. Worked Example N — De Morgan’s AND transformation
For A=1,B=0, NOT(A AND B)=1. (NOT A) OR (NOT B)=0 OR 1=1. Verify the full table to prove equivalence.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
24. Worked Example O — De Morgan’s OR transformation
For A=0,B=0, NOT(A OR B)=1. (NOT A) AND (NOT B)=1 AND 1=1. The gate type changes when the entire expression is negated.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
25. Worked Example P — Double negation
NOT(NOT A)=A regardless of whether A is zero or one. Two inversions cancel.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
26. Worked Example Q — AND identity
A AND 1=A. Adding an always-true condition does not change A’s value.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
27. Worked Example R — OR identity
A OR 0=A. Adding an always-false alternative does not change the original signal.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
28. Worked Example S — AND annulment
A AND 0=0 for either value of A. A permanently false input prevents a true AND output.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
29. Worked Example T — OR annulment
A OR 1=1. The true alternative makes the overall condition true regardless of A.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
30. Worked Example U — Idempotent AND and OR
A AND A=A and A OR A=A. Repeating the same condition does not introduce a different requirement.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
31. Worked Example V — XOR self-cancellation
A XOR A=0. The two inputs are always equal by construction, so exclusive OR never fires.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
32. Worked Example W — NAND as inversion
A NAND A=NOT A, because A AND A=A and the output is inverted.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
33. Worked Example X — NOR as inversion
A NOR A=NOT A, because A OR A=A and NOR negates the result.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
34. Worked Example Y — A useful Boolean identity
(A AND B) OR (A AND NOT B)=A. Factor A, then recognise B OR NOT B is one; the entire expression reduces to A.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
35. Worked Example Z — An original three-input decision
For the fictitious classroom status expression (A AND B) OR C, A=1 booking active, B=0 teacher absent, C=0 demonstration flag off. Output is zero. The example teaches traceable logic, not a real access-control design.
Check the input combination, intermediate gate, negation if any, and final output. For an equivalence claim, a single matching row is not enough; compare all possible rows.
36. Gate names encode exact truth conditions
AND, OR, NAND, NOR, XOR and NOT have different response patterns. Remember the question being asked, not only the symbol’s appearance.
37. OR and XOR differ in a critical row
Both return one on 0/1 and 1/0; only OR returns one on 1/1. That row is a decisive diagnostic.
38. Output bubbles invert the whole result
NAND is NOT(A AND B) and NOR is NOT(A OR B). Inverting just one input creates a different function.
39. Two inputs need four rows
There are 2×2 combinations. Three binary inputs create 2×2×2=8 possibilities, and all must be checked.
40. Parentheses matter
A AND(B OR C) differs from (A AND B) OR C for some inputs. Use intermediate results and explicit grouping.
41. De Morgan’s laws flip AND and OR
NOT(A AND B)=(NOT A) OR (NOT B), while NOT(A OR B)=(NOT A) AND (NOT B). Negate both operands.
42. An output table is a definition of the function
Two gate networks are equivalent only when all rows match. One mismatched row disproves equality.
43. Boolean and ordinary arithmetic are different
Logical OR may be shown as a plus sign, but Boolean A OR A=A, unlike ordinary A+A when A is one.
44. Simplification must preserve output
Reducing the number of gates can make a circuit easier to read, but only if the original logical function is unchanged.
45. Input semantics are part of correctness
An input flag meaning ‘closed’ must not be silently treated as ‘open’ in a later circuit sketch.
46. Real devices require engineering safeguards
Classroom gate examples are not sufficient to design physical locks, alarms or emergency systems.
47. Independent transfer is the goal
A student should explain verbal rules, build a circuit or expression, and verify it with a table on an unseen context.
48. Misconception Ledger
- Assuming inclusive OR and XOR produce the same result for inputs 1/1.
- Forgetting that NAND and NOR invert the complete gate output.
- Using seven rows in a three-input truth table instead of eight.
- Changing the meaning of A halfway through a circuit question.
- Dropping parentheses and altering the circuit.
- Treating Boolean OR as ordinary arithmetic addition.
- Calling two circuits equal after checking one row.
- Applying De Morgan’s theorem without flipping the gate operator.
- Simplifying an expression without testing that the output stays identical.
- Using a paper logic exercise as a real safety-system design.
49. Three-Pupil Gate Workshop
Student A translates written requirements into input definitions and Boolean expressions. Student B calculates gate outputs and constructs the truth table. Student C audits rows and uses counterexamples to challenge false equivalence. Rotate roles, then independently complete a new three-input problem with different variable names.
50. eduKate Depth–Load–Transfer Diagnostic
Depth: reconstruct all six gate truth rules, including OR versus XOR, without notes. Load: combine AND, NOT, OR and an eight-row table while keeping the grouping clear. Transfer: model an unfamiliar fictional library status flag, then identify whether two proposed circuits agree in every row. Classify errors as gate, input, inversion, grouping, row, simplification or interpretation.
51. Independent Practice and Answers
Test these: XOR(1,1)=0; NOR(0,0)=1; NAND(1,0)=1; NOT(0)=1; (1 AND 0) OR 1=1; A AND 1=A; A XOR A=0; NOT(1 AND 0)=1 and (NOT 1) OR (NOT 0)=1. For each, state the law or gate rule and then complete a fresh truth table.
52. Parent and Tutor Questions
Ask ‘How many rows are required?’, ‘Which gate is calculated first?’, ‘Where is the inversion applied?’, ‘Does OR include both true?’, ‘Can you find a counterexample?’, ‘What happens when A changes but B stays fixed?’, and ‘Are these expressions equivalent on all inputs?’ These questions expose genuine understanding.
53. Frequently Asked Questions
What are the six prescribed gates?
AND, OR, NOT, NAND, NOR and XOR, with their symbols and truth tables.
How many circuit inputs are examined?
The K349 syllabus states a maximum of three inputs in the relevant problems.
What distinguishes XOR from OR?
XOR returns one when exactly one of its two inputs is one; OR returns one when either or both are one.
What does NAND do?
It inverts the complete AND output.
What does NOR do?
It inverts the complete OR output.
Why are truth tables useful?
They inspect all combinations and can prove or disprove Boolean equivalence.
What is De Morgan’s first law?
NOT(A AND B)=(NOT A) OR (NOT B).
What is De Morgan’s second law?
NOT(A OR B)=(NOT A) AND (NOT B).
Is the example a real safety or access system?
No. It is a fictional binary logic exercise only.
54. Closing Principle
Define the inputs, recognise the gates, preserve parentheses and verify every combination. Once students can prove two Boolean circuits equivalent—or disprove them with one row—they can reason independently about computing logic rather than memorise drawings.
Related eduKateSG References and Official Sources
Read Reference 301 — Binary Data Representation, Reference 203 — Algorithms and Flowcharts, Reference 314 — Computing Security and Privacy, the MOE V3.0 reference library, the immutable Clementi teaching benchmark and official 2027 K349 Computing, Module 1.3.
MOE V3.0 Reference Sequence Navigation
Previous reference 320 · MOE V3.0 reference library. Complete a new circuit without its answers to confirm independent transfer.