A semiconductor company succeeds when a designed chip becomes a traceable, usable and dependable component in a customer’s product. A successful tape-out, a full wafer or a high production count does not by itself prove that the chips pass their required tests or will keep performing in service.
This guide follows HarbourSilica Microdevices, a wholly fictional Singapore chip company developing a small industrial sensor interface integrated circuit. It designs the chip, contracts wafer fabrication, and relies on specialist partners for packaging and final testing. After a supplier process change, a higher proportion of parts fail final inspection even though wafer probing looks normal. The team must establish what changed, what stock is affected and how to keep customer commitments without releasing uncertain components.
The Gold Standard master hub defines excellence through management and repeatable execution. Related articles cover Semiconductors as a discipline, Manufacturing Companies as factory operators, and Precision Engineering for measurement. This article instead follows the company responsible for design, suppliers, qualified products, commercial risk and lasting customer support.
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Follow a single fictional chip from design to wafer test, assembly, sale and customer feedback. Use the grouped index when you need a specific stage.
Chapter index
Business model, specifications and design · Chapters 1–5
- Know which semiconductor business model the company operates
- Start product requirements with the real application
- Keep design revisions and verification evidence together
- Protect intellectual property without trapping technical knowledge
- Choose foundries and packaging suppliers by capability, not price alone
Process, yield and qualification · Chapters 6–12
- Treat process changes as a qualification event when relevant
- Read wafer yield correctly before using it as a success claim
- Use failure categories to find the true weak step
- Keep assembly and final test tied to production identity
- Validate reliability for the intended service conditions
- Keep measurement systems calibrated and data reproducible
- Protect fabrication and test workers through competent EHS controls
Safety, resources and lawful trade · Chapters 13–15
Supply, economics and customer outcomes · Chapters 16–18
1. Know which semiconductor business model the company operates
A fabless chip designer, integrated device manufacturer, wafer foundry, assembly-and-test company and equipment supplier perform different activities. They have different capital requirements and may never own the same part of a product’s history. A commercial promise must identify which firm designed the device, which facilities built and tested it, and who accepts the final quality decision.
HarbourSilica owns the chip design but does not own the wafer fabrication plant or packaging lines. Its directors maintain a responsibility map for wafer data, process changes, test coverage, delivery and field complaints. When the final-test yield falls, an email to ‘the factory’ is not an adequate response: the issue could arise in design, fabrication, assembly, measurement or handling. Clear ownership is necessary to identify the fault.
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2. Start product requirements with the real application
Chips are embedded in vehicles, appliances, telecommunications equipment, industrial controls and other systems with different consequences of failure. The company needs a defined electrical function, operating conditions, interfaces, reliability requirements and customer acceptance criteria. A part that operates on an engineer’s bench may not be suitable for every intended deployment.
HarbourSilica develops a fictional sensor interface for industrial monitoring. It should state what signals it accepts, its relevant operating envelope, the supported package and what it does not claim. Product management must not advertise it as qualified for safety-critical applications without the appropriate evidence. Sales should work from the approved product specification rather than invent technical promises for a major customer.
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3. Keep design revisions and verification evidence together
Integrated circuit design involves specifications, architecture, simulation, layout, verification and manufacturing files. Design errors can survive many successful intermediate checks, especially when the test plan does not address a relevant operating condition. The company needs review gates, version records and a way to relate each manufactured lot to the approved design release.
HarbourSilica’s design team records the version used for its wafer order and the evidence supporting release to manufacture. A later mask or firmware-related revision must be assessed against the existing product and customer commitments. A design that passed one simulation is not automatically fully verified. Management should ask what requirements were actually checked and where uncertainty remains.
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4. Protect intellectual property without trapping technical knowledge
A semiconductor enterprise may depend on intellectual-property blocks, electronic design tools, libraries, manufacturing process information and partner agreements. Rights and licence restrictions need to be understood before reuse. At the same time, keeping design decisions solely in one engineer’s private files creates operational fragility.
HarbourSilica maintains approved access, source provenance and documentation sufficient for authorised team members to reproduce important verification findings. Confidentiality does not justify losing the basis for a quality decision. Supplier contracts should clarify ownership of design files, test programmes, masks and the data needed to investigate defects. Long-term maintainability is an asset, not merely an administrative cost.
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5. Choose foundries and packaging suppliers by capability, not price alone
A foundry’s available process, capacity, quality systems, change-notice practices and commercial lead times all affect a chip company’s risks. Assembly houses and test providers have equally important obligations. A purchasing comparison based only on price per wafer can hide differences in yield, access to data and the cost of delayed deliveries.
Singapore’s Economic Development Board semiconductor overview describes the local value chain from IC design and wafer fabrication to advanced packaging and testing. HarbourSilica assesses which partners can perform the specific processes and qualifications needed. It should not describe any supplier as fully interchangeable merely because both advertise the same broad manufacturing category.
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6. Treat process changes as a qualification event when relevant
A manufacturer may change a material, equipment, location, process parameter or subcontractor. Not every change affects the product, but some can influence its electrical performance or reliability. A company must understand notification obligations, compare evidence and decide whether additional tests or customer approvals are required.
HarbourSilica receives a process-change notice after the affected lot has already entered assembly. Engineering and quality personnel determine its scope, trace the included wafer lots and assess the tests needed before product disposition. The company should not assume all parts are faulty; equally it must not release them on the grounds that wafer-sort results look familiar. A supplier’s assurance needs a traceable technical basis.
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7. Read wafer yield correctly before using it as a success claim
A wafer can contain many individual die, each tested or assessed against different criteria. A wafer’s physical production does not establish how many sellable components will remain after probing, assembly and final test. Yield metrics should identify exactly which stage and denominator they describe.
For an invented example, HarbourSilica has 1,000 candidate die and 780 pass wafer sort. The wafer-sort yield is 78%. Those 780 units may still face damage, assembly issues or final electrical tests. Management should not report 780 commercially releasable chips merely because a test map shows that many passing sites. The relevant figure for customer supply is the verified output at the specified final acceptance stage.
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8. Use failure categories to find the true weak step
Yield can fall for multiple reasons: defective die, packaging problems, contamination, handling, unsuitable tests or a genuine design sensitivity. Grouping everything into ‘failed parts’ limits what engineers can learn. The company needs appropriately controlled bin definitions and traceability between test conditions and physical product.
HarbourSilica finds most new failures after packaging, while wafer-sort performance remains stable. A good investigation compares approved test methods, package lots, wafer histories and any authorised process changes. It does not automatically blame the packaging contractor. A meaningful defect investigation should identify supported hypotheses, evidence that would challenge them and qualified people authorised to decide disposition.
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9. Keep assembly and final test tied to production identity
Packaging and assembly introduce materials, process operations and further electrical checks. Devices often pass through several legal entities and locations before they become shipped components. Losing wafer or assembly lot identity can turn a contained problem into a far larger customer disruption.
HarbourSilica’s quality system links the final unit or shipment lot to the appropriate design, wafer, assembly and testing records. It should distinguish a test programme change from an actual product change. A shipment described as approved must be supported by the current specification and authorised release criteria. If traceability is lost, the company needs an honest assessment of which inventory can still be supplied.
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10. Validate reliability for the intended service conditions
A chip can pass an immediate electrical test but show weaknesses under time, temperature, mechanical or environmental stresses relevant to its intended use. Reliability qualification should be designed by qualified specialists and interpreted against the product’s requirements. No one accelerated test proves infinite field life.
HarbourSilica’s industrial sensor interface is evaluated under a technical qualification plan approved for its actual use. When a process change raises uncertainty, the team determines which reliability evidence remains applicable. The company may need a narrower claim or additional testing. Reliability is a managed scientific judgement supported by data, not an advertising label attached because one prototype operated for weeks.
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11. Keep measurement systems calibrated and data reproducible
Semiconductor testing depends on probes, handlers, instruments, fixtures, software and reference standards. A drift in measurement equipment or an unrecorded test-programme revision can create apparent yield changes without an equivalent change in the chips. Conversely, a weak measurement system can fail to detect a real defect.
HarbourSilica checks the status of test equipment and the software revision before judging two suppliers’ data comparable. Quality staff should preserve raw findings and appropriately authorised corrections. The Precision Engineering guide explains measurement traceability. At company level, the priority is making decisions from trustworthy, comparable records rather than accepting whichever measurement gives the most convenient result.
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12. Protect fabrication and test workers through competent EHS controls
Semiconductor manufacturing can involve specialised machinery, electrical systems and chemicals whose hazards require qualified facility and process safeguards. Requirements depend on the operation. A company should not treat a clean-looking production room as proof that every relevant exposure or equipment hazard is controlled.
SEMI safety standards include S2 for semiconductor manufacturing equipment, S8 for ergonomics and S10 for risk assessment, alongside other specific guidance. Singapore’s MOM risk-management requirements cover workplace hazards. HarbourSilica reviews its own premises and supplier oversight proportionately, while leaving technical safety decisions to qualified people.
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13. Treat electricity, water and materials as production dependencies
Wafer fabrication and related operations may require dependable power, high-quality process water, controlled facilities and sophisticated equipment. Utility constraints affect operating costs and production plans. Environmental efficiency measures must not be judged solely by a lower utility bill if they undermine product quality or transfer risk to another part of the supply chain.
Singapore EDB highlights industrial infrastructure, talent and utility systems in its semiconductor industry information. HarbourSilica should understand the dependencies in its contracted manufacturing capacity without implying it directly operates the foundry. A company can reduce avoidable energy, water and material waste while preserving validated process conditions through appropriately qualified oversight.
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14. Manage strategic goods and technology transfers lawfully
Some semiconductor goods, equipment, software and know-how may be subject to export or technology-transfer controls. Classification depends on actual specifications, destination, intended use and relevant legal rules. Not every chip is a strategic good, and not every controlled transfer is limited to physical packages crossing a border.
Singapore Customs explains controls over listed goods and intangible technology transfers, along with catch-all provisions. The Strategic Goods (Control) Order 2026 has been announced with an effective date of 1 December 2026, after this article’s 17 October date. HarbourSilica should use the rules applicable on the actual transaction date and obtain qualified determination rather than assuming a customer order is sufficient authority.
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15. Make supply commitments reflect real capacity and risk
Semiconductor products can have long lead times, dedicated manufacturing steps and suppliers that are difficult to replace quickly. The company should distinguish forecast demand, accepted orders, allocated manufacturing capacity, tested inventory and shipped goods. When demand changes, a new sales forecast does not instantly create available chips.
HarbourSilica’s buyer requests an extra 2,000 parts before a factory shutdown. The sales team should check qualified available inventory and real supplier capacity before promising a date. Alternative sources or packages may require technical review and customer acceptance. A good supply plan includes credible buffers and a route for explaining disruptions without implying every planned lot is already production-ready.
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16. Handle quality complaints with complete lot history
A customer may report intermittent failure long after a shipment. The supplier needs a reliable way to connect the device marking, order, production genealogy, approved conditions and prior complaint patterns. A claim may require specialised testing and cooperation with several suppliers, not an immediate assignment of blame.
HarbourSilica’s service desk logs the customer’s observed symptoms without making unsupported technical claims. Competent staff investigate relevant samples and compare them with affected production records. If the issue could have wider implications, management considers appropriate containment and communication. A company that discards obsolete test files when a product revision ends may be unable to investigate failures fairly.
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17. Budget design, yield loss and the product’s full commercial life
A fabless business pays for design tools, intellectual property, engineering, foundry production, packaging, tests, logistics and support. Wafer price and total die count are insufficient to calculate its profitable output. The economics can change sharply when final-good yield falls or expensive rescreening is needed.
HarbourSilica’s fictional batch starts with 1,000 die; 780 pass wafer sort and 720 meet the final product tests. Final-good yield relative to the starting die is 72%, while wafer-sort yield is 78%. The 60-part difference between those stages needs investigation and cost allocation. Management should calculate margin using actual sellable devices and all relevant costs, not divide the wafer invoice by every fabricated die.
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18. The gold standard is a dependable chip and an accountable company
HarbourSilica’s yield anomaly is repaired only after the company identifies what changed, verifies which production lots are affected, determines qualified product disposition, explains customer implications and updates its process-change controls. It should also confirm whether the problem could recur at another packaging partner.
The gold standard for semiconductor companies is not a boast about a tiny feature size or an unusually full wafer. It is reproducible engineering, traceable production, safe partners, lawful technology transfer, honest yield measures and real support for customers who depend on the chip. Consistent governance connects innovation with reliable supply.
Worked chip yield: wafer passes are not the finished shipment
These are fictional numbers for understanding the denominator. They are not a typical fab yield, process benchmark or quality-release criterion.
| Stage | Illustrative count | What it proves |
|---|---|---|
| Starting candidate die | 1,000 | Initial die count, not saleable output |
| Pass wafer sort | 780 | 780 ÷ 1,000 = 78% at wafer sort |
| Pass final accepted tests | 720 | 720 ÷ 1,000 = 72% final-good yield |
| Difference between stages | 60 | Requires investigation; not automatically a single supplier’s fault |
| Available for customer allocation | Subject to authorised release | A measured pass alone is not commercial approval |
Semiconductor company directors’ checklist
- What does the company design, manufacture, outsource and support?
- Can each shipped lot be traced to approved design and supplier revisions?
- Are wafer-sort, final-test and field-return measures reported separately?
- Is every process change examined for its impact on qualification?
- Are test equipment, programmes and data versioned and controlled?
- Do foundry, packaging and test suppliers have clear escalation responsibilities?
- Are worker safety and utilities accounted for without unqualified claims?
- Has strategic goods classification been reviewed for actual exports or intangible transfers?
- Can the company support customers after a product reaches end-of-life?
Official and industry references with eduKate connections
- Singapore EDB: Semiconductor Industry — design, fabrication, packaging and testing ecosystem
- SEMI: Semiconductor Equipment Safety Standards — equipment, personnel and process hazards
- MOM: Workplace Risk Management — workplace hazard assessment
- Singapore Customs: Strategic Goods Control — controlled trade and technology transfer
- Singapore Customs: Determination of Strategic Goods — specification-based classification
- eduKate: The Gold Standard of Semiconductors — process and supply discipline
- eduKate: Manufacturing Companies — company-level quality systems
This educational company-management guide is not chip-design instructions, a semiconductor qualification protocol, strategic-goods legal advice or product certification. The fictional company and numerical yield example do not describe a real chip or commercial factory. Apply the current laws and technical rules for each actual product and market.