SG Z6 VL-OS Registry Pack v0.1 — Verification Literacy (AI-Era Anti-Brittleness Spine)

TITLE: SG Z6 VL-OS Registry Pack v0.1 — Verification Literacy (AI-Era Anti-Brittleness Spine)
VERSION: CivOS Unified Spec v1.x
MODE: Almost-Code / Copyable blocks / WordPress paste-ready
OWNER: eduKateSG Fence Learning Systems
PLACE: SG
ZOOM: Z6
GOAL: Specify the full Verification Literacy OS (VL-OS) as a standalone lane:
      - NodeRegistry (VL core capabilities)
      - SignatureRegistry (AI-era failure patterns)
      - ProtocolRegistry (truncate + stitch + widen)
      So every lane (ENG/MATH/SCI/HUM) is protected against AI-brittleness.
LOCKS:
- VL-OS is cross-lane and mandatory.
- No widening allowed if TracePresent=no.
- Every protocol must include retest + exit conditions.
========================================================
REGISTRY-0: VERSION HEADER
========================================================
UnifiedSpecVersion: v1.x
VLRegistryVersion: v0.1
Place: SG
Zoom: Z6
Owner: eduKateSG Fence Learning Systems
Updated: 2026-02-16
Status: live
========================================================
REGISTRY-1: NodeRegistry — SG×VL (CORE) v0.1
========================================================
Schema:
VLNode := {
  id, title, level_band, status,
  prereq_nodes[], output_nodes[],
  sensors[], signatures[],
  protocols[], tags[]
}
Records:
- id: SG×VL×Z0×Learner×Node×VL-CHECK-BASIC
  title: Basic Check Types (substitute / estimate / unit-check / contradiction)
  level_band: P3–JC
  status: active
  prereq_nodes: []
  output_nodes: [SG×VL×Z0×Learner×Node×VL-TRACE-LINE]
  sensors: [SG×VL×Z6×Tutor×Sensor×SENS-VL-MICRO-10]
  signatures: [SG×VL×Z6×Operator×Signature×SIG-AI-VL-01]
  protocols: [SG×VL×Z6×Operator×Protocol×PROT-VL-CHECK-TRAIN]
  tags: ["core","anti-brittleness"]
- id: SG×VL×Z0×Learner×Node×VL-TRACE-LINE
  title: Trace Line (show 1-line verification)
  level_band: P3–JC
  status: active
  prereq_nodes: [SG×VL×Z0×Learner×Node×VL-CHECK-BASIC]
  output_nodes: [SG×VL×Z0×Learner×Node×VL-SPOT-WRONG]
  sensors: [SG×VL×Z6×Tutor×Sensor×SENS-VL-MICRO-10]
  signatures: [SG×VL×Z6×Operator×Signature×SIG-AI-VL-02]
  protocols: [SG×VL×Z6×Operator×Protocol×PROT-VL-TRACE-ENFORCE]
  tags: ["trace","mandatory"]
- id: SG×VL×Z0×Learner×Node×VL-SPOT-WRONG
  title: Spot Wrong (identify plausible but incorrect reasoning)
  level_band: P4–JC
  status: active
  prereq_nodes: [SG×VL×Z0×Learner×Node×VL-TRACE-LINE]
  output_nodes: [SG×VL×Z0×Learner×Node×VL-VARIATION-TRANSFER]
  sensors: [SG×VL×Z6×Tutor×Sensor×SENS-VL-MICRO-10]
  signatures: [SG×VL×Z6×Operator×Signature×SIG-AI-VL-03]
  protocols: [SG×VL×Z6×Operator×Protocol×PROT-VL-SPOT-WRONG]
  tags: ["false-competence","robustness"]
- id: SG×VL×Z0×Learner×Node×VL-VARIATION-TRANSFER
  title: Variation Transfer (apply under slight change)
  level_band: Sec1–JC
  status: active
  prereq_nodes: [SG×VL×Z0×Learner×Node×VL-SPOT-WRONG]
  output_nodes: []
  sensors: [SG×SCI×Z6×Tutor×Sensor×SENS-TT-V-SCI]
  signatures: [SG×VL×Z6×Operator×Signature×SIG-AI-VL-04]
  protocols: [SG×VL×Z6×Operator×Protocol×PROT-VL-VARIATION-DRILL]
  tags: ["transfer","anti-shortcut"]
========================================================
REGISTRY-2: SignatureRegistry — SG×VL v0.1
========================================================
Schema:
VLSignature := {
  id, name, severity_class,
  markers[], typical_context,
  linked_nodes[], recommended_protocol
}
Records:
- id: SG×VL×Z6×Operator×Signature×SIG-AI-VL-01
  name: Blind Acceptance of Tool Output
  severity_class: S3
  markers: [
    "no checking step",
    "cannot explain answer",
    "changes answer when tool changes"
  ]
  typical_context: "AI-assisted homework; calculator reliance"
  linked_nodes: [SG×VL×Z0×Learner×Node×VL-CHECK-BASIC]
  recommended_protocol: SG×VL×Z6×Operator×Protocol×PROT-VL-CHECK-TRAIN
- id: SG×VL×Z6×Operator×Signature×SIG-AI-VL-02
  name: Trace Missing
  severity_class: S3
  markers: [
    "no working shown",
    "no evidence line",
    "no unit-check"
  ]
  typical_context: "all lanes"
  linked_nodes: [SG×VL×Z0×Learner×Node×VL-TRACE-LINE]
  recommended_protocol: SG×VL×Z6×Operator×Protocol×PROT-VL-TRACE-ENFORCE
- id: SG×VL×Z6×Operator×Signature×SIG-AI-VL-03
  name: False Competence (recognition not production)
  severity_class: S2
  markers: [
    "can choose MCQ but cannot explain",
    "fails on open-ended variation"
  ]
  typical_context: "exam mini sets"
  linked_nodes: [SG×VL×Z0×Learner×Node×VL-SPOT-WRONG]
  recommended_protocol: SG×VL×Z6×Operator×Protocol×PROT-VL-SPOT-WRONG
- id: SG×VL×Z6×Operator×Signature×SIG-AI-VL-04
  name: Transfer Collapse Under Variation
  severity_class: S2
  markers: [
    "works for template only",
    "fails when numbers/context shift"
  ]
  typical_context: "structured application"
  linked_nodes: [SG×VL×Z0×Learner×Node×VL-VARIATION-TRANSFER]
  recommended_protocol: SG×VL×Z6×Operator×Protocol×PROT-VL-VARIATION-DRILL
========================================================
REGISTRY-3: ProtocolRegistry — SG×VL v0.1
========================================================
Schema:
VLProtocol := {
  id, name,
  truncation_steps[],
  stitching_steps[],
  retest_plan[],
  exit_conditions[]
}
Records:
- id: SG×VL×Z6×Operator×Protocol×PROT-VL-CHECK-TRAIN
  name: Check-Type Drill Protocol
  truncation_steps: [
    "ban final answer without named check type",
    "reduce problem size to 5 items",
    "force 1-line estimation or substitution"
  ]
  stitching_steps: [
    "increase variation gradually",
    "alternate check types"
  ]
  retest_plan: [
    "SENS-VL-MICRO-10 in 3 days",
    "repeat weekly until 2 passes"
  ]
  exit_conditions: [
    "TracePresent=yes in 2 consecutive cycles",
    "No SIG-AI-VL-01 markers"
  ]
- id: SG×VL×Z6×Operator×Protocol×PROT-VL-TRACE-ENFORCE
  name: Trace Enforcement Protocol
  truncation_steps: [
    "reject answers without trace",
    "limit to 3 problems with full trace"
  ]
  stitching_steps: [
    "add time constraint gradually",
    "combine with lane sensor"
  ]
  retest_plan: [
    "SENS-VL-MICRO-10 next session"
  ]
  exit_conditions: [
    "TracePresent=yes 2 cycles",
    "ERC_repeat=0"
  ]
- id: SG×VL×Z6×Operator×Protocol×PROT-VL-SPOT-WRONG
  name: Spot-Wrong Contrast Protocol
  truncation_steps: [
    "show 2 similar answers (1 wrong, 1 correct)",
    "ask learner to justify which is correct"
  ]
  stitching_steps: [
    "increase similarity between answers",
    "remove labels gradually"
  ]
  retest_plan: [
    "Mini variation set within 1 week"
  ]
  exit_conditions: [
    "Learner explains why wrong is wrong",
    "FalseCompetence flag cleared"
  ]
- id: SG×VL×Z6×Operator×Protocol×PROT-VL-VARIATION-DRILL
  name: Variation Drill Protocol
  truncation_steps: [
    "reduce complexity; change only one parameter",
    "force re-derivation"
  ]
  stitching_steps: [
    "increase parameter shifts",
    "mix lanes (ENG→SCI reasoning)"
  ]
  retest_plan: [
    "Use TT-V-SCI or EXAM-MINI variant"
  ]
  exit_conditions: [
    "TR>=70 under variation",
    "No SIG-AI-VL-04 markers"
  ]
========================================================
REGISTRY-4: REQUIRED FAILURE TRACE (VL-OS)
========================================================
Trace:
Tool accepted blindly →
no trace →
plausible wrong passes →
variation collapse →
exam failure.
Repair:
Check type discipline →
trace enforcement →
spot-wrong contrast →
variation drill →
transfer stability →
AI-era robustness.
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END: SG Z6 VL-OS Registry Pack v0.1
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